Staff Logic Design Engineer

Teledyne is seeking a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture, analysis, and emulation on FPGA-based test and measurement systems.

Responsibilities

• Develop synthesizable RTL (Verilog, SystemVerilog) for high-speed protocol parsing, timestamping, and buffer management
• Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency
• Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, place-and-route, timing closure, and resource optimization
• Integrate PCIe IP cores, DMA engines, and custom protocol decoders
• Build SystemVerilog and UVM testbenches for block and system-level verification
• Conduct simulation, waveform analysis, and functional coverage
• Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms
• Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA, SignalTap)
• Create design specifications, interface documents, and verification plans

Requirements

• BS in EE, CS, or Computer Engineering required; MS in EE is a plus
• 7+ years of experience in digital logic design for FPGA or ASIC
• Strong proficiency in Verilog and SystemVerilog RTL design
• Experience with one or more of: PCIe, CXL, NVMe, USB, SAS, SATA
• Experience with monitoring or test and measurement tools
• Experience with PCIe protocol (Gen4, Gen5, Gen6) and familiarity with TLP, DLLP, and PHY layer concepts
• Hands-on with FPGA toolchains (Vivado, Quartus) and timing closure
• Knowledge of UVM, assertions, and simulation and debug tools (ModelSim, Vivado Simulator)
• Solid understanding of CDC, clock domain design, and reset strategies

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